BANDGAP VOLTAGE REFERENCE USING TRIPLE CASCODE OPERATIONAL AMPLIFIER
DOI:
https://doi.org/10.55766/sujst8390Keywords:
Bandgap Voltage Reference, Gain, Miller compensation, MOSFET, PM, Temperature coefficient, Triple Cascode Op-AmpAbstract
Bandgap Voltage reference (BGR) circuits are crucial components in analog circuits. In this paper, a BGR circuit capable of obtaining a reference voltage of 1.0435 V is proposed. In the proposed BGR circuit, Miller compensated two-stage Triple Cascode Operational Amplifier (Op-Amp) has been used which achieves a higher gain of 104.1db and Phase Margin of 73.78 degrees with 1.8V supply voltage using 90nm technology. The proposed BGR circuit achieves 4.51 ppm/OK of temperature coefficient and 0.4375 mV/V of line regulation. The designed BGR circuit can be used in analog applications.
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