INVESTIGATING DOUBLE GATE LITHIUM NIOBATE-BASED METAL FERROELECTRIC METAL INSULATOR SEMICONDUCTOR (MFMIS) NCFETS THROUGH ANALYTICAL MODELING AND SIMULATION
DOI:
https://doi.org/10.55766/sujst-2024-05-e06156Keywords:
Ferroelectric materials, Lithium Niobate, L-K theory, MFMIS architecture, NCFET, Silicon CircuitAbstract
As the miniaturization of silicon circuits continues, the primary challenge has shifted towards reducing energy consumption. The Boltzmann limit, a fundamental barrier in traditional semiconductor devices, has prompted the exploration of novel solutions. One promising candidate is the Negative Capacitance Field Effect Transistor (NCFET). NCFETs introduce a second insulating ferroelectric material to create a negative capacitance (CFE) effect, which counteracts the positive capacitances inherent in Field Effect Transistors (FETs). This interaction allows for lower operating voltages and enhanced energy efficiency. Silicon, a ubiquitous material in semiconductor devices, remains a focal point of this research due to its widespread use and well-understood properties. Extensive analytical studies have been conducted on silicon-based devices, examining their performance at ever-decreasing nanoscale gate levels. This work presents a significant advancement with the introduction of high-performance LiNbO3-based NCFETs. Compared to traditional single-gate designs, the proposed LiNbO3-based NCFET demonstrates superior performance metrics. Notably, it exhibits hysteresis-free characteristics, leading to a more stable and efficient operational region. The absence of hysteresis not only simplifies the device’s operation but also enhances its reliability and scalability for future applications. In conclusion, the implementation of LiNbO3-based NCFETs represents a promising step towards overcoming the limitations imposed by the Boltzmann limit, offering a pathway to more energy-efficient silicon circuits as they continue to shrink in size.
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