DESIGN AND ANALYSIS OF NOVEL PARALLEL PREFIX ADDERS FOR VLSI CIRCUITS
DOI:
https://doi.org/10.55766/sujst-2024-01-e0379Keywords:
ALU, Han Carlson Adder, Brent Kung, PPA, Kogge Stone AddersAbstract
Arithmetic Logic Unit is the brain of all processors, is composed of an Adder circuit. The main component of multiplier circuits is the adder, which performs subtraction (by 2’s complement arithmetic). Since the most fundamental operation in mathematics is addition, and the adder is the most essential part of the processor, the study of VLSI arithmetic has required many digital VLSI researchers. When designing digital systems employing the VLSI approach, the digital adder plays a major role. Low power VLSI based adder designs perform poorly because of the propagation delay issue. With the aid of the PPA design, an assessment of adders’ availability for low power VLSI designs with minimal propagation delay is conducted. Using these performance measures, this study compares and evaluates the performance of several parallel prefix adders, allowing readers to select the optimum adder architecture for their application Specific Integrated Circuits implementations. The three adder topologies taken into considered in this Article include the Han carlson adder, Brent kung, Kogge stone adders. Xilinx ZYNQ XC7Z020 (7000 series) SoC is used to implement the adders using the Vivado Design Suite 2014 and Verilog.
References
Bais, K. and Ali, Z. (2016). Comparison of Various Adder Designs in terms of Delay and Area. International Journal of Science and Research, 2013:1,292-1,296.
Cho S.M., Meher, P.K., Trung, L.T.N., Cho, H.J., and Park, S.Y. (2021), Design of Very High-Speed Pipeline FIR Filter Through Precise Critical Path Analysis. IEEE Access, 9: 34,722-34,735. https://doi.org/10.1109/ACCESS.2021.3061759
Daphni, S. and Grace, K.S.V. (2017). A review analysis of parallel prefix adders for better performnce in VLSI applications IEEE International Conference on Circuits and Systems (ICCS), 103-106.
Hoe, D.H.K. Martinez, C. and Vundavalli, S.J. (2011). Design and Characterization of Efficient Parallel Prefix Adders using FPGAs. 2011 IEEE 43rd Southeastern Symposium on System Theory. https://doi.org/10.1109/SSST.2011.5753800
Kaneko M. (2019). A Novel Framework for Procedural Construction of Parallel Prefix Adders. IEEE International Symposium on Circuits and Systems (ISCAS). https://doi.org/10.1109/ISCAS.2019.8702117
Macedo, M., Soares, L., Silveira, B., Diniz, C.M., Costa E.A.C. (2017). Exploring the use of parallel prefix adder topologies into approximate adder circuits. IEEE International Conference on Electronics, Circuits and Systems (ICECS), 298-301. https://doi.org/10.1109/ICECS.2017.8292078
Moghaddam, M. and Ghaznavi-Ghoushchi M.B. (2011). A New Low-Power, Low-area, Parallel Prefix Sklansky Adder with Reduced Inter-Stage Connections Complexity. 2011 IEEE EUROCON - International Conference on Computer as a Tool. https://doi.org/10.1109/EUROCON.2011.5929280
Rahila K.C, Kumar U.S. (2019). A Comprehensive Comparative Analysis of Parallel Prefix Adders for ASIC Implementation. International Conference on System Energy And Environment, 1-5.
Sudhakar, S.M., Chidambaram K.P., and Swartzlander E.E. (2012). Hybrid Han-Carlson Adder. Midwest Symposium on Circuits and Systems (MWSCAS), 818-821. https://ieeexplore.ieee.org/document/6292146
Thakur, G., Sohal, H., and Jain, S., (2020). FPGA-Based Parallel Prefix Speculative Adder for Fast Computation Application. 2020 Sixth International Conference on Parallel, Distributed and Grid Computing (PDGC), 206-210. https://doi.org/10.1109/PDGC50313.2020.9315783
Venkata, V., Visweswara, S., Ramachandram, S., and Amulya, P. (2019). Performance Comparison Among Various Parallel Prefix Adder Topologies, Journal of Engineering Sciences, 10(1):342-346.
Vitoroulis, K., and Al-Khalili, A.J. (2007). Performance of Parallel Prefix Adders implemented with FPGA technology. Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS), 498-501. https://doi.org/10.1109/NEWCAS.2007.4487969
Xiang, L.M., Zabidi, M.M.A., Awab, A.H., Rahman, A.A.H.A. (2018). VLSI Implmentation of a Fast Kogge-Stone Parallel-Prefix Adder. Journal of Physics: Conference Series, 1049 (2018):012077. https://doi.org/10.1088/1742-6596/1049/1/012077
Yezerla, S.K. and Naik, B.R. (2014). Design and estimation of delay, power and area for Parallel prefix adders. Recent Advances in Engineering and Computational Sciences (RAECS). https://doi.org/10.1109/RAECS.2014.6799654
Zamhari, N., Voon, P., Kipli, K., Chin, K.L. and Husin M.H. (2012). Comparison of Parallel Prefix Adder (PPA). Proceedings of the World Congress on Engineering 2012 Vol II.
