AREA EFFICIENT ARCHITECTURE FOR WAVE DIGITAL ELLIPTIC FILTER USING-LEVEL TRANSFORMATIONS
Wave digital elliptic filter
DOI:
https://doi.org/10.55766/sujst-2024-04-e01955Keywords:
DSP architectures, folding, high-level transformation techniques, retimingAbstract
Digital filters are important blocks of low frequency signal processing especially biomedical signals. They are the integral algorithm of digital signal processing (DSP). Multiplier, adder and delay are the major three parts of digital filter out of which multiplier is the maximum power and area consuming part. When implemented in a custom or semi-custom reconfigurable digital logic device, complexity will be more with multipliers than adders. Again functional units like adders and multipliers increased with the higher order of filter. Novel architecture for wave digital elliptic filters (WDEF) using folding and retiming, which are the high-level transformation techniques, is proposed. The basic elements of the filter from a data flow graph (DFG)are properly scheduled to reduce the number of multipliers and adders. The designed folded filter architecture is synthesised and implemented on Xilinx ML605 (XC6VLX240T1FFG1156 FPGA) embedded development kit. The criterions considered for optimization are power consumption and minimum hardware area. A comparison is done between the folded architecture and the conventional architecture which shows that there is 92.31% reduction in the used number of adders and 87.5% reduction in the used number of multipliers. The performance comparison shows that the designed architecture is more efficient with single adder and multiplier unit. The synthesis result shows that there is reduction of 85.39% for logic cells and of 92.31% for DSP slice in terms of area utilization for folded & conventional structures. Again the power consumption is reduced by 49.25% for folded and conventional architectures.
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