GEOMETRIC INVESTIGATION AND PERFORMANCE ANALYSIS OF SOI FINFET FOR RF/AF PARAMETERS
Keywords:
Terms-Silicon On Insulator (SOI), Radio Frequency (RF), TCAD tool, FinFET, Voltage GainAbstract
FinFET-based devices provide better and faster operational performance and, thus, are widely preferred to be integrated into a complex circuit application. The present paper has proposed a silicon on insulator (SOI) FinFET and studies the effect of hfin variations (1.3,1.0,0.7,0.25) and Wfin variations (1.0,0.6,0.25) on structure performance metrics, counting low-frequency limitations such as transconductance (Gm), output conductance (Gd), capacitances and voltage gain (Av). The structure clearly shows excellent efficiency for (i) ππππ/π³π = 0.7 figure by increasing device gain and operational frequency; (ii) πΎπππ/π³π = 0.6 figure by optimizing structure intrinsic resistance, AV, and VEA, thereby making the device perform without even any substrate impact, according to simulations conducted using the SILVACO tool. The investigation has identified that structure length variation could provide varied performances, such as higher device-current being recommended for improved current drivability and smaller devices being preferred for reducing SCEs and increasing device immunization. The current study can serve as a starting point for 3-D device simulators looking to attain improved performance.
References
Choi, Y. K., Asano, K., Lindert, N., Subramanian, V., King, T. J., Bokor, J., & Hu, C. (1999, December). Ultra-thin body SOI MOSFET for deep-sub-tenth micron era. In International Electron Devices Meeting 1999. Technical Digest (Cat. No. 99CH36318) (pp. 919-921). IEEE.
Hisamoto, D., Lee, W. C., Kedzierski, J., Takeuchi, H., Asano, K., Kuo, C., & Hu, C. (2000). FinFET-a self-aligned double-gate MOSFET scalable to 20 nm. IEEE transactions on electron devices, 47(12), 2320-2325.
Morris, D.H., Avci, U.E. and Young, I.A., Intel Corp, U.S. Patent Application 15/992, 080, 2019.
Wadhwa, G., & Raj, B. (2019). Design, simulation and performance analysis of JLTFET biosensor for high sensitivity. IEEE Transactions on Nanotechnology, 18, 567-574.
Hisamoto, D., Lee, W. C., Kedzierski, J., Takeuchi, H., Asano, K., Kuo, C., ... & Hu, C. (2000). FinFET-a self-aligned double-gate MOSFET scalable to 20 nm. IEEE transactions on electron devices, 47(12), 2320-2325.
Wadhera, T., Kakkar, D., Wadhwa, G., & Raj, B. (2019). Recent advances and progress in development of the field effect transistor biosensor: a review. Journal of Electronic Materials, 48(12), 7635-7646.
Kumar, A., Gupta, N., Tripathi, S. K., Tripathi, M. M., & Chaujar, R. (2020). Performance evaluation of linearity and intermodulation distortion of nanoscale GaN-SOI FinFET for RFIC design. AEU-International Journal of Electronics and Communications, 115, 153052.
Voldman, S., Hui, D., Warriner, L., Young, D., Williams, R., Howard, J., Gross, V., Rausch, W., Leobangdung, E., Sherony, M. and Rohrer, N., In 1999 IEEE International SOI Conference. Proceedings (Cat. No. 99CH36345), pp. 68-71, 1999, October. IEEE.
Pradhan, K. P., Mohapatra, S. K., Sahu, P. K., & Behera, D. K. (2014). Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET. Microelectronics journal, 45(2), 144-151.
Chhabra, A., Kumar, A., & Chaujar, R. (2019). Sub-20 nm GaAs junctionless FinFET for biosensing application. Vacuum, 160, 467-471.
Subramanian, V., Mercha, A., Parvais, B., Loo, J., Gustin, C., Dehan, M., & Decoutere, S. (2007). Impact of fin width on digital and analog performances of n-FinFETs. Solid-State Electronics, 51(4), 551-559.
Narendar V, Rai S, Tiwari S (2016) A two-dimensional (2D) analytical surface potential and subthreshold current model for underlap dual-material double-gate (DMDG) FinFET. J Computational Electron 15(4):1316β1325
Narendar, V., Rai, S., Tiwari, S., & Mishra, R. A. (2016). A two-dimensional (2D) analytical subthreshold swing and transconductance model of underlap dual-material double-gate (DMDG) MOSFET for analog/RF applications. Superlattices and Microstructures, 100, 274- 289.
Chhabra, A., Kumar, A., & Chaujar, R. (2018, February). GaAs Junctionless FinFET using Si3N4 Spacer for High performance Analog Application. In 2018 International Conference On Advances in Communication and Computing Technology (ICACCT) (pp. 483-486). IEEE.
Yanagi, S. I., Nakakubo, A., & Omura, Y. (2001). Proposal of a partial-ground-plane (PGP) silicon-on-insulator (SOI) MOSFET for deep sub-0.1-ΞΌm channel regime. IEEE Electron Device Letters, 22(6), 278-280.
Lolivier, J., Widiez, J., Vinet, A., Poiroux, T., Dauge, F., Previtali, B. & Deleonibus, S. (2004, September). Experimental comparison between double gate, ground plane, and single gate SOI MOSFETs. Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No. 04EX850) (pp. 77-80). IEEE.
Kumar, M. J., & Siva, M. (2008). The ground plane in buried oxide for controlling short-channel effects in nanoscale SOI MOSFETs. IEEE Transactions on Electron Devices, 55(6), 1554-1557.
Ashaf, A., Tyagi, M., & Mani, P. (2018). To study high-performance analysis of surround gate SOI MOSFET. International Journal of Engineering & Technology, 7(2.8), 191-194.
de Andrade, M. G. C., Martino, J. A., Aoulaiche, M., Collaert, N., Simoen, E., & Claeys, C. (2012). The behavior of triple-gate Bulk FinFETs with and without DTMOS operation. Solid-state electronics, 71, 63-68.
Amrouch, H., Pahwa, G., Gaidhane, A. D., Dabhi, C. K., Klemme, F., Prakash, O., & Chauhan, Y. S. (2020). Impact of variability on processor performance in negative capacitance finfet technology. IEEE Transactions on Circuits and Systems I: Regular Papers, 67(9), 3127-3137.
Kumar, A., Chhabra, A., & Chaujar, R. (2018, April). GaAs junctionless FinFET using high-k dielectric for high-performance applications. In 2018 IEEE 38th International Conference on Electronics and Nanotechnology (ELNANO) (pp. 126-129). IEEE.
Gupta, N., & Kumar, A. (2020). Assessment of High-k Gate Stack on Sub-10 nm SOI-FinFET for High-Performance Analog and RF Applications Perspective. ECS Journal of Solid State Science and Technology, 9(12), 123009.
Kumar, B., Kumar, A., & Chaujar, R. (2020, July). The Effect of Gate Stack and High-ΔΈ Spacer on Device Performance of a Junctionless GAA FinFET. In 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) (pp. 159-163). IEEE.
