DESIGN OF 4-BIT PARTIAL PRODUCTS PARTITIONING ADDER WITH HIGH SPEED AND LOW POWER DELAY PRODUCT

Bhaskara  Rao Doddi; Hari  Kanaka Raghu Vamsi Kudulla; Vandana  Mahanthi

Authors

Bhaskara Rao Doddi Faculty of ECE, Raghu Engineering College(A), Visakhapatnam, India.
Hari Kanaka Raghu Vamsi Kudulla Faculty of ECE, Raghu Engineering College(A), Visakhapatnam, India.
Vandana Mahanthi Faculty of ECE, Raghu Engineering College(A), Visakhapatnam, India

Keywords:

Adder, speed, power delay product, partial products

Abstract

Adder has been designed with uniquely designed XNOR and carry cells for every4bits. InLook ahead structure, generate and propagate are designed in inverting methodology unlike the conventional ones. This will give a more parallel structure to reduce the delay, as partial products were partitioned. Proposed adder has reported better results when compared to the many existing designs in the recent literature with respect to power, delay and power delay product. Delay analysis for every block is done by estimating the critical paths for the events in the output by determining the strongly charged and discharged paths. Power analysis has been done by activating the possible power-consuming transitions for every block in the circuit. Tanner EDAtool has been used with 250 nm technology.

References

Aguirre-Hernandez, M. and Linares-Aranda, M. (2011). CMOS full-adders for energy-efficient arithmetic applications. IEEE Transactions on Verylarge Scale Integration (VLSI) Systems, 19(4):4.

Bhattacharya, P., Kundu, B., Ghosh, S., Kumar, V., and Dandapat, A. (2015). Performance analysis of a low-power high-speed hybrid 1-bit full adder circuit. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(10):8.

Chang, C.H., Gu, J., and Zhang, M. (2005). A review of 0.18-μm full adder performances for treestructured arithmetic circuits. IEEE Transactionson Very Large Scale Integration. (VLSI) Systems, 13(6):10.

Chowdhury, S.R., Banerjee, A., Roy, A., and Saha, H. (2008). A high speed 8 transistor full adder design using novel 3 transistor XOR gates. Int. J. Elect. Cir. Sys, 2(4):7.

Hamed, N. and Somayeh, T. (2018). Low-power and fast full adder by exploring new XOR and XNOR gates. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(8):13.

Hasan, M., Hossein, M.J., Hossain, M., Zaman, and H.U., Islam, S. (2020). Design of a scalable low-power 1-bit hybrid full adder for fast computation. IEEE Transactions On Circuits And Systems -II: Express Briefs, 67(8):5.

Hassoune, I., Flandre, D., O’Connor, I., and Legat,J.D. (2010). ULPFA: A new efficient designof apower-aware full adder. IEEE Transactions on Circuits Systems. I, Reg. Papers, 57(8):9.

Kandpal, J., Tomar, A., Agarwal, M., and Sharma, K.K. (2020). High-speed hybrid-logic full adder using high-performance 10-T XOR-XNOR cell. IEEE transactions on VLSI systems, 28(6):10.

Kumar, P. and Sharma, R.K. (2016). Low voltage high performance hybrid full adder. Engineering. Sci. Technol. Int. J., 19(1):7.

Miao, J. and Li, S. (2017). A novel implementation of 4-bit carry look-ahead adder. In: International Conference On Electron Devices And Solid-State Circuits (EDSSC), Oct 18-20, Hsinchu, Taiwan, p. 2.

Mohanty, B.K. and Patel, S.J. (2014). Area-delay-power efficient carry-select adder. IEEE Transactions on Circuits and Systems-II: Express Briefs, 61(6):5.

Parameshwara, M.C. and Srinivasaiah, H.C. (2017). Low- Power Hybrid 1-Bit Full-Adder Circuit for Energy Efficient Arithmetic Applications. Journal of Circuits, Systems, and Computers, 26(1):1750014.

Vesterbacka, M. (1999). A 14-transistor CMOS fulladder with full swing nodes. In: Proc. IEEE Workshop on Signal Process. Systems; 22-22 Oct, 1999; Taipei, Taiwan, p. 10.

Wairya, S., Nagaria, R.K., and Tiwari, S. (2011). New design methodologies for high-speed low- voltage 1 bit CMOS Full Adder circuits. Int. J. Comput. Technol. Appl, 2(2):9.

Weste, N. and Eshraghian, K. (1985). Principles of CMOS VLSI Design. New York, NY, USA: Addison-Wesley, 713p.