DESIGN AND ANALYSIS OF ELECTRICAL CHARACTERISTICS OF INVERTED-T JUNCTIONLESS (JL) FET THROUGH GEOMETRIC AND PROCESS VARIATIONS FOR HIGH FREQUENCY APPLICATIONS

Authors

  • sameeksha Munjal -
  • neelam rup Prakash
  • Jasbir Kaur
  • komal .

DOI:

https://doi.org/10.55766/sujst-2023-06-e01131

Keywords:

Analog performance, Inverted-T junctionless transistor, process variation, short channel effects

Abstract

An inverted-T structure is implemented with the Junctionless (JL) topology at nanoscale dimensions. The Inverted-T Junctionless (ITJL) FET features a multi-fin architecture that utilizes the unused space within the fins and combines it with the junctionless topology, maintaining the same doping concentration from source to drain. In order to mitigate the short channel effects and overcome the fabrication challenges, an inverted-T FET has been designed. The crucial performance parameters of device are explored by varying the geometric dimensions and process parameters. The performance of ITJLFET is measured by varying different parameters namely temperature (T), doping concentration (Nd), work function 𝒎 ), and dielectric constant (K) at 30-nm technology node and effect of geometric variations are measured by altering the gate length (Lg) and oxide thickness (Tox). Inverted-T junctionless field effect transistor (ITJLFET) is designed with different gate lengths in the range of 14 nm to 30 nm and shows the improvement in ION by 64% as compared to the conventional JLFET. The parametric analysis like transfer characteristics (Id-Vgs), Ion/IOFF ratio, subthreshold swing (SS), drain induced barrier lowering (DIBL) and gate capacitance (Cgg) are investigated for 250 K to 350 K. From the results, it is perceived that temperature has less effect on the Inverted-T junctionless transistor performance. The cut-off frequency for the designed device is calculated and observed to be in the range of 0.3 to 1.5 THz. Hence, device can be used for high-frequency applications at the submicron regime.

References

Agnihotri, P. and Tripathi, N. (2019). Junctionless transistors for future applications. International Journal of Information Technology and Electrical Engineering, 8(4):50-53. https://doi.org/10.13140/RG.2.2.32152.88322.

Andricacos, P.C., Uzoh, C., Dukovic J.O., Horkans, J., and Deligianni, H. (1998). Damascene copper electroplating for chip interconnections. IBM Journal of Research and Development, 42(5):567-574. https://doi.org/10.1147/ rd.425.0567

Bagga, N., Kumar, A., Bhattacharjee, A., and Dasgupta, S. (2017). Performance evaluation of a novel GAA schottky junction (GAASJ) TFET with heavily doped pocket. Superlattices and Microstructure, 109:545-552. https://doi.org/10.1016/j.spmi.2017.05.040

Bashir, M.Y., Raushan, M.A., Ahmad, S., and Siddiqui M.J. (2022). Investigation of gate material engineering in junctionless transistor for digital and analog applications. Silicon, 14:2851-2862. https://doi.org/10.1007/s12633-021-01066-8

Bharath, S.V. and Narendar, V. (2021). Design and deep insights into Sub-10 nm spacer engineered junctionless FinFET for nanoscale applications. ECS Journal of Solid State Science and Technology, 10:013008. https://doi.org/10.1149/ 2162-8777/abddd4

Bhuyan, M.H. (2017). History and evolution of CMOS technology and its application in semiconductor industry. SEU Journal of Science and Engineering, 11(1):30-42.

Bohr, M.T. (1995). Interconnect scaling-the real limiter to high performance ULSI. In: Proceedings of International Electron Devices Meeting, p. 241-244. https://doi.org/ 10.1109/IEDM.1995.499187

Cheng, B., Cao, M., Rao, R., Inani, A., Vande Voorde, P., Greene, W.M., Stork, J.M.C., Zhiping, Y., Zeitzoff, P.M., and Woo, J.C.S. (1999). The impact of high-k gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs. IEEE Transactions on Electron Devices, 46(7):1537-1544. https://doi.org/10.1109/16.772508

Choi, S.J., Moon, D.I., Kim, S., Duarte, J.P., and Choi, Y.K. (2011). Sensitivity of threshold voltage to nanowire width variation in junctionless transistors. IEEE Electron Device Letters, 32(2):125-127. https://doi.org/10.1109/LED.2010. 2093506

Cogenda Pvt Ltd. (2008). Singapore, Genius, 3-D Device Simulator, Version 1.9.3, Reference Manual, Singapore.

Colinge, J.P. (2012). Junctionless transistors. 2012 IEEE International Meeting for Future of Electron Devices, Kansai, Suita, Japan, p. 1-2, https://doi.org/10.1109/ IMFEDK.2012.6218561

Colinge, J.P., Lee, C.W., Afzalian, A., Akhavan, N.D., Yan, R., Ferain, I., Razavi, P., O'Neill, B., Blake, A., White, M., Kelleher, A.M., McCarthy, B., and Murphy, R. (2010). Nanowire transistors without junctions. Nature Nanotechechnology, 5:225-229. https://doi.org/10.1038/ nnano.2010.15

Colinge, J.P., Lee, C.W., Akhavan, N.D., Yan, R, Ferain, I., Razavi, P., Kranti, A., and Yu, R. (2011). Junctionless transistors: physics and properties. Semiconductor on Insulator Materials and Nanoelectronics Application, p. 187-200. https://doi.org/10.1007/978-3-642-15868-1_10

Fahad, H.M., Hu, C., and Hussain, M.M. (2015). Simulation study of a 3-D device integrating FinFET and UTBFET. IEEE Transactions on Electron Devices, 62(1):83-87. https://doi.org/10.1109/TED.2014.2372695

International Technology Roadmap for Semiconductors (ITRS), (2015). Semiconductor Industry Association. [Online]. Available: https://www.semiconductors.org/resources/2015-international-technology-roadmap-for-semiconductors-itrs/

Jeon, D.Y. (2020). Simple estimation of intrinsic electrical parameters in junctionless transistors. AIP Advances, 10(9):095118. https://doi.org/10.1063/5.0022769

Kaushik, B.K., Goel, S., and Rauthan, G. (2007). Future VLSI interconnects: Optical fiber or carbon nanotube - A review. Microelectronics International, 24(2):53-56. https://doi.org/ 10.1108/13565360710745601

Kuhn, K.J., Avci, U., Cappellani, A., Giles, M.D., Haverty, M., Kim, S., Kotlyar, R., Manipatruni, S., Nikonov, D., Pawashe, C., Radosavljevic, M., Rios, R., Shankar, S., Vedula, R., Chaua, R., and Young, I. (2012). The ultimate CMOS device and beyond. In: 2012 International Electron Devices Meeting, San Francisco, USA, p. 8.1.1-8.1.4. https://doi.org/10.1109/IEDM.2012.6479001

Kumar, R. and Kumar, A. (2021a). Hafnium based high-k dielectric gatestacked (GS) gate material engineered (GME) junctionless nanotube MOSFET for digital applications. Applied Physics A, 127:26. https://doi.org/ 10.1007/s00339-020-04217-7

Kumar, R. and Kumar, A. (2021b). Hetro-Dielectric (HD) Oxide- Engineered Junctionless Double Gate all around (DGAA) Nanotube Field Effect Transistor (FET). Silicon, 13:2177-2184. https://doi.org/10.1007/s12633-020-00705-w

Lilienfeld, J.E., Inventor; Individual, Current Assignee. 1925. Method and Apparatus for Controlling Electric Currents. U.S. patent no. US1745175A.

Lilienfeld, J.E., Inventor; Individual, Current Assignee. 1928. Device for Controlling Electric Current Filed. U.S. patent no. US1900018A.

Ma, Y., Sweis, J., Bencher, C., Deng, Y., Dai, H., Yoshida, H., Gisuthan, B., Kye, J., and Levinson, H. (2011). Double patterning compliant logic design. In: Proceedings of SPIE - The International Society for Optical Engineering, San Jose, United States, Volume 7974, https://doi.org/10.1117/ 12.879846

Matick, R.E. and Schuster, S.E. (2005). Logic-based eDRAM: Origins and rationale for use. IBM Journal of Research and Development, 49(1):145-165. https://doi.org/10.1147/ rd.491.0145

Moore, G.E. (1965). Cramming more components onto integrated circuits. Electronics Magazine, 38:114-117.

Nelapati, R.P. and K., S. (2020). Process variation study of SELBOX inverted- T junctionless FinFET for high-performance applications. Silicon, 12:1699-1706. https://doi.org/10.1007/s12633-019-00270-x

Pal, P.K, Kaushik, B.K., and Dasgupta, S. (2014). Investigation of symmetric dual-k spacer trigate FinFETs from delay perspective. IEEE Transactions on Electron Devices, 61(11):3579-3585. https://doi.org/10.1109/TED.2014. 2351616

Park, H. and Choi, B. (2012). A study on the performance of metal-oxide-semiconductor-field-effect-transistors with asymmetric junction doping structure. Current Applied Physics, 12(6):1503-1509. https://doi.org/10.1016/j.cap. 2012.04.026

Paz, B.C., Pavanello, M.A., Cassé, M., Barraud, S., Reimbold, G., Faynot, O., Avila-Herrera, F., and Cerdeira, A. (2015). From double to triple gate: Modeling junctionless nanowire transistors. In: EUROSOI-ULIS 2015: 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, Bologna, Italy, p. 5-8. https://doi.org/10.1109/ULIS.2015.7063759

Sahay, S. and Kumar M.J. (2019a). Fundamentals of junctionless field‐effect transistors. In: Junctionless Field-Effect Transistors: Design, Modeling, and Simulation, Sahay, S. and Kumar, M.J. (eds.). Wiley Online Library, p. 67-123. https://doi.org/10.1002/9781119523543.ch3

Sahay, S. and Kumar, M.K. (2019b). Introduction to field‐effect transistors. In: Junctionless Field-Effect Transistors: Design, Modeling, and Simulation, Sahay, S. and Kumar, M.J. (eds.). Wiley Online Library, p. 1-26. https://doi.org/ 10.1002/9781119523543.ch1

Schuegraf, K., Abraham, M.C., Brand, A., Naik, M., and Thakur, R. (2013). Semiconductor logic technology innovation to achieve sub-10 nm manufacturing. IEEE Journal of the Electron Devices Society, 1(3):66-75, https://doi.org/ 10.1109/JEDS.2013.2271582

Shankar, R., Kaushal, G., Maheshwaram, S., Dasgupta, S., and Manhas, S.K. (2014). A degradation model of double gate and gate-all-around mosfets with interface trapped charges including effects of channel mobile charge carriers. In: IEEE Transactions on Device and Materials Reliability, 14(2):689-697. https://doi.org/10.1109/TDMR.2014.2310292

Trevisoli, R.D., Doria, R.T., Souzad, M., and Pavanello, M.A. (2011). Threshold voltage in junctionless nanowire transistors. Semiconductor Science and Technology, 21(10):1015009. https://doi.org/10.1088/0268-1242/26/10/ 105009

Vadthiya, N. and Mishra, R.A. (2015). Analytical modeling and simulation of multigate FinFET devices and the impact of high-k dielectrics on short channel effects (SCEs). Superlattices and Microstructures, 85:357-369. https://doi.org/ 10.1016/j.spmi.2015.06.004

Vadthiya, N., Narware, P., Bheemudu, V., and Sunitha, B. (2020). A novel bottom-spacer ground-plane (BSGP) FinFET for improved logic and analog/RF performance. AEU - International Journal of Electronics and Communications, 127:153459. https://doi.org/10.1016/ j.aeue.2020.153459

Vakkalakula, B.S. and Vadthiya, N. (2021). Design and temperature assessment of junctionless nanosheet FET for nanoscale applications. Silicon, 14:3823-3834 https://doi.org/10.1007/s12633-021-01145-w

Vandana, B., Das, J.K., Mohapatra, S.K., and Jyothi, M.S. (2017). Impact on gate oxide material of inverted ‘T’ junctionless FinFET at 22 nm technology node. In: 2017 1st International Conference on Electronics, Materials Engineering and Nano-Technology (IEMENTech), Kolkata, India, p. 1-5. https://doi.org/10.1109/IEMENTECH. 2017.8076957

Vandana, B., Patro, B.S., Das, J.K., Kaushik, B.K., and Mohapatra, S.M. (2018). Inverted ‘T’ junctionless FinFET (ITJL FinFET): performance estimation through device geometry variation. ECS Journal of Solid States Science and Technology, 7(4):52-59. https://doi.org/10.1149/ 2.0071804jss

Wong, H.S.P., Frank, D.J., and Solomon, P.M. (1998). Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation. In: International Electron Devices Meeting 1998. Technical Digest (Cat. No. 98CH36217), San Francisco, CA, USA, p. 407-410. https://doi.org/10.1109/IEDM.1998.746385

Yoda, H., Fujita, S., Shimomura, N., Kitagawa, E., Abe, K., Nomura, K., Noguchi, H., and Ito, J. (2012). Progress of STT-MRAM technology and the effect on normally-off computing systems. 2012 International Electron Devices Meeting, San Francisco, CA, USA, p. 11.3.1-11.3.4. https://doi.org/10.1109/IEDM.2012.6479023

Zhang, W., Fossum, J.G., and Mathew, L. (2006) The ITFET: A novel FinFET-based hybrid device. IEEE Transactions on Electron Devices, 53(9):2335-2343. https://doi.org/10.1109/ TED.2006.880813

Downloads

Published

2024-02-21

How to Cite

Munjal, sameeksha, rup Prakash , neelam, Kaur, J., & ., komal. (2024). DESIGN AND ANALYSIS OF ELECTRICAL CHARACTERISTICS OF INVERTED-T JUNCTIONLESS (JL) FET THROUGH GEOMETRIC AND PROCESS VARIATIONS FOR HIGH FREQUENCY APPLICATIONS. Suranaree Journal of Science and Technology, 30(6), 010267(1–12). https://doi.org/10.55766/sujst-2023-06-e01131