DESIGN OF AREA & POWER EFFICIENT MGDI FULL ADDER USING POWER GATING TECHNIQUE
DOI:
https://doi.org/10.55766/sujst-2024-04-e01061Keywords:
CMOS, GDI, MGDI, PG-MGDIAbstract
Full adders are utilized in many different appeals, in digital signal processors, microprocessors & microcontrollers, and are an essential component of the design of many digital systems. Great control is needed in electronic devices and circuits, which necessitates low power and rapid processing. The power gated MGDI complete full adder style analysis and design are displayed. Some low power complexity is retained in this entire adder. The presentation and appeal of MGDI full adder with existing adders, such as GDI and M-GDI. The solution of the power gated- MGDI full-adder demonstrated better power analysis values. Low power dissipation is decreased by using the MGDI Method while designing circuits. A MGDI approach enhances the threshold voltage drop and overcomes weak voltage swing output. Power gating is a method used in IC design to minimize power utilization by switching off the current to this circuit lumps, that are bared. The entire adder was constructed utilizing 45 nm technology and the Cadence tool's toggle drawing mode. It is based on the Power Gated- MGDI. The solution of power analysis obtained is 17.61uW & delay of 21.25e-9. It achieved 96.07%,87.6%,87.3, 83.7% & 78.8% for Conventional full adder,10T-GDI, 16T-Hybrid, 14T-MVT-GDI and 8T-M-GDI Technique. It achieved delay of 89.5%, 50%,50.5%93% &17.95% for Conventional full adder,10T-GDI, 16T-Hybrid, 14T-MVT-GDI and 8T-M-GDI Technique. The construction of full adders for effective arithmetic operations and the installation of MASH and modulators for Sigma Delta DACs are two contemporary applications of the GDI technique that are also examined in this work.
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