B. Rao Doddi, H. Kanaka Raghu Vamsi Kudulla, and V. Mahanthi, “DESIGN OF 4-BIT PARTIAL PRODUCTS PARTITIONING ADDER WITH HIGH SPEED AND LOW POWER DELAY PRODUCT”, Suranaree J Sci Technol, vol. 29, no. 5, pp. 010155(1–11), Aug. 2026.