Rao Doddi, B., Kanaka Raghu Vamsi Kudulla, H. and Mahanthi, V. (2026) “DESIGN OF 4-BIT PARTIAL PRODUCTS PARTITIONING ADDER WITH HIGH SPEED AND LOW POWER DELAY PRODUCT”, Suranaree Journal of Science and Technology, 29(5), pp. 010155(1–11). available at: https://ph04.tci-thaijo.org/index.php/SUJST/article/view/15169 (accessed: 11 September 2026).