RAO DODDI, B.; KANAKA RAGHU VAMSI KUDULLA, H.; MAHANTHI, V. DESIGN OF 4-BIT PARTIAL PRODUCTS PARTITIONING ADDER WITH HIGH SPEED AND LOW POWER DELAY PRODUCT. Suranaree Journal of Science and Technology, [S. l.], v. 29, n. 5, p. 010155(1–11), 2026. Disponível em: https://ph04.tci-thaijo.org/index.php/SUJST/article/view/15169. Acesso em: 16 sep. 2026.