Rao Doddi, B., Kanaka Raghu Vamsi Kudulla, H., & Mahanthi, V. (2026). DESIGN OF 4-BIT PARTIAL PRODUCTS PARTITIONING ADDER WITH HIGH SPEED AND LOW POWER DELAY PRODUCT. Suranaree Journal of Science and Technology, 29(5), 010155(1–11). retrieved from https://ph04.tci-thaijo.org/index.php/SUJST/article/view/15169